The structure and layout of machine instructions that the CPU executes
Instruction formats in computer architecture define the structure and layout of machine instructions that the CPU executes. They specify how operations and operands are encoded within the binary instructions, guiding the processor on how to fetch, decode, and execute each instruction.
How instructions are laid out in binary
How operations and operands are represented
Directs fetch, decode, and execute processes
Instruction formats are crucial for defining the instruction set architecture (ISA) of a processor, determining its capabilities and compatibility with software. They form the foundation of how software communicates with hardware.
Defines the operation to be performed by the CPU. Typically occupies a fixed portion of the instruction word. Examples include arithmetic operations (add, subtract), data movement (load, store), and control flow (jump, branch).
Data or addresses on which the operation acts. Can be specified in various ways depending on the addressing mode (immediate, direct, indirect, register, etc.). Operand fields may vary in size and position within the instruction format.
Specifies how to interpret or compute the operand address. Directly impacts how operands are fetched from memory or registers. Can be part of the opcode or in a separate field within the instruction format.
Flags or control information that governs the execution behavior of the instruction. Includes condition codes, interrupt enable/disable, privilege levels, etc.
All instructions have the same length in bits. Simplifies instruction fetching and decoding but may lead to inefficient use of space for simpler instructions.
Instructions vary in length based on the complexity of the operation or addressing mode. Efficient for compact instruction sets but requires more complex decoding logic.
Allows operations with three operands. Useful for complex arithmetic operations and scientific computing.
Typically used in older architectures where one operand serves as both a source and destination. Limited flexibility but efficient for certain operations.
Operates on data stored in one register. Often used in stack-based or accumulator-based architectures.
Instruction formats aim to balance between compactness and flexibility, optimizing instruction decoding and execution.
Formats must support a wide range of operations and addressing modes specified by the ISA.
Instructions must be encoded efficiently to minimize memory usage and maximize execution speed.
Defines the size and structure of machine instructions. Determines how instructions are fetched, decoded, and executed by the CPU. Can be fixed-length or variable-length depending on the architecture.
Instruction length determines how many bytes need to be fetched from memory
Format complexity affects the decoding logic and time required
Structure determines how operands are accessed and processed
Specifies the operation to be performed (addition, subtraction, load, store, etc.). The opcode is a fixed set of bits that tells the CPU what operation to execute.
Hold data or addresses required for the operation. Format includes fields for different addressing modes (immediate, direct, indirect, etc.).
// Typical instruction format structure
|----------------|----------------|----------------|
| Opcode | Operand 1 | Operand 2 |
|----------------|----------------|----------------|
// Or with addressing mode field:
|----------------|----------------|----------------|----------------|
| Opcode | Addressing Mode| Operand 1 | Operand 2 |
|----------------|----------------|----------------|----------------|
| Aspect | Fixed-Length Instructions | Variable-Length Instructions |
|---|---|---|
| Definition | All instructions are of the same size in bits | Instructions vary in size based on complexity or addressing modes |
| Advantages | Simplifies instruction fetching and decoding | Efficient use of memory for simpler instructions |
| Disadvantages | May waste space for simpler instructions | Requires more complex decoding logic |
| Examples | RISC architectures (ARM, MIPS) | CISC architectures (x86) |
The choice between fixed-length and variable-length instructions involves trade-offs between simplicity of decoding (fixed-length) and efficient use of memory (variable-length). Fixed-length instructions simplify processor design but may waste memory space, while variable-length instructions optimize memory usage but require more complex decoding mechanisms.
Operates on three operands. Useful for complex arithmetic operations and scientific computing. Example: ADD R1, R2, R3 means R1 ← R2 + R3.
Uses one operand for both source and destination. Limited flexibility but efficient for certain operations. Example: ADD R1, R2 means R1 ← R1 + R2.
Operates on data stored in one register. Often used in stack-based or accumulator-based architectures. Example: ADD R1 means ACC ← ACC + R1.
// Three-address format (common in RISC)
ADD R1, R2, R3 // R1 = R2 + R3
SUB R4, R5, R6 // R4 = R5 - R6
// Two-address format (common in CISC)
ADD R1, R2 // R1 = R1 + R2
SUB R3, R4 // R3 = R3 - R4
// One-address format (accumulator-based)
LOAD R1 // ACC = R1
ADD R2 // ACC = ACC + R2
STORE R3 // R3 = ACC
Translating assembly language mnemonics into machine code. Involves mapping opcodes and operands to binary representations.
Converting human-readable instructions to binary
Assigning binary values to operation codes
Process of interpreting machine code instructions for execution by the CPU. The control unit decodes the instruction to determine what operation to perform and where to find the operands.
Retrieving instruction from memory
Retrieving operands based on addressing mode
Low-level instructions directly executable by the CPU. Binary representation of operations and data movements.
Composed of 0s and 1s that the CPU directly interprets
No translation needed; CPU can execute directly
Unique to each processor architecture
// x86 machine language example
// Assembly: ADD AX, BX
// Machine code: 01 D8 (in hexadecimal)
// Binary: 00000001 11011000
// ARM machine language example
// Assembly: ADD R0, R1, R2
// Machine code: E0810001 (in hexadecimal)
// Binary: 11100000100000010000000000000001
Human-readable mnemonics representing machine instructions. Translated into machine code by an assembler.
Short, readable codes representing operations (ADD, SUB, MOV, etc.)
Different assembly languages for different processors
Must be assembled into machine code before execution
// x86 assembly example
MOV AX, 5 ; Move immediate value 5 into AX register
ADD AX, BX ; Add BX to AX
MOV [SI], AX ; Store AX at memory location pointed to by SI
// ARM assembly example
LDR R0, =5 ; Load immediate value 5 into R0
ADD R1, R0, R2 ; R1 = R0 + R2
STR R1, [R3] ; Store R1 at memory location pointed to by R3
Specifies how arithmetic instructions (addition, subtraction, multiplication, division) are structured. Includes opcode, operand fields for source and destination registers or memory locations.
| Operation | Mnemonic | Description |
|---|---|---|
| Addition | ADD | Adds two operands and stores result |
| Subtraction | SUB | Subtracts second operand from first |
| Multiplication | MUL | Multiplies two operands |
| Division | DIV | Divides first operand by second |
// Three-address format
ADD R1, R2, R3 // R1 = R2 + R3
SUB R4, R5, R6 // R4 = R5 - R6
// Two-address format
ADD R1, R2 // R1 = R1 + R2
SUB R3, R4 // R3 = R3 - R4
// One-address format (accumulator-based)
ADD R2 // ACC = ACC + R2
SUB R3 // ACC = ACC - R3
Defines structure for logical operations (AND, OR, XOR, NOT). Similar to arithmetic operations but with different opcodes.
| Operation | Mnemonic | Description |
|---|---|---|
| AND | AND | Bitwise AND operation between operands |
| OR | OR | Bitwise OR operation between operands |
| XOR | XOR | Bitwise exclusive OR operation |
| NOT | NOT | Bitwise NOT operation (complement) |
// Three-address format
AND R1, R2, R3 // R1 = R2 AND R3
OR R4, R5, R6 // R4 = R5 OR R6
XOR R7, R8, R9 // R7 = R8 XOR R9
// Two-address format
AND R1, R2 // R1 = R1 AND R2
OR R3, R4 // R3 = R3 OR R4
// One-address format (accumulator-based)
AND R2 // ACC = ACC AND R2
OR R3 // ACC = ACC OR R3
How data is moved between registers, memory, and I/O devices. Includes opcodes for load (from memory to register) and store (from register to memory) operations.
| Operation | Mnemonic | Description |
|---|---|---|
| Load | LD, LDR, MOV | Load data from memory to register |
| Store | ST, STR, MOV | Store data from register to memory |
| Move | MOV, MV | Move data between registers or memory |
| Exchange | XCHG, SWP | Exchange contents of two locations |
// Load operations
LDR R0, [R1] // Load R0 with contents of memory at R1
MOV AX, [BX] // Load AX with contents of memory at BX
// Store operations
STR R2, [R3] // Store R2 to memory at R3
MOV [SI], CX // Store CX to memory at SI
// Move operations
MOV R4, R5 // Move R5 to R4
MOV R6, #10 // Move immediate value 10 to R6